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MDT10P41A1
1. General Description
This EPROM-Based 8-bit Micro-controller uses a fully static CMOS technology to achieve high speed, small size, low power and high noise immunity. Internal RC oscillator On chip memory includes 1K words of EPROM, and 31 bytes of static RAM. transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy,
automobile and PC peripheral ... etc.
4. Pin Assignment
2. Features
u u u u Fully CMOS static design 8-bit data bus On chip ROM size :1 K words Internal RAM size : 31 bytes (25 general purpose registers, 6 special registers) u u u u u 34 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3V ~ 5.5 V Addressing modes include direct, indirect and relative addressing modes u u u Power-on Reset Internal RC oscillator : 6.5MHz ~ 7.5MHz 12 I/O pins with their own independent direction control
MDT10P41A1P / MDT10P41A1S
PB4 PB5 PB6 PB7 Vdd NC NC PA0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 PB3 PB2 PB1 PB0 Vss PA3 PA2 PA1
3. Applications
The application areas of this MDT10P41A1 range from appliance motor control and high speed automotive to low power remote
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 1 of 11 2005/6 Ver.1.6
MDT10P41A1
5. Block Diagram
Stack Two Levels
10 bits
EPROM 1024N14
14 bits
RAM 25N8 Port A
Port PA0~PA3 4 bits
10 bits
Program Counters
Instruction Register Special Register
Port PB0 D0~D7 Port PB1
Port B Instruction Decoder Internal RC
Data 8bit
Port PB2~PB3
Port PB4 ~PB7
Control Circuit
Power on Reset Power Down Reset Working Register Status Register ALU
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 2 of 11 2005/6 Ver.1.6
MDT10P41A1
6. Pin Function Description
Pin Name PA0 PA1~PA3 I/O I/O I/O Function Description Open drain ouput pin with 130K ohm pull-high resistor for input. Port A, TTL input level. PA1-PA3 are I/O pins with 50K ohm pull-high resistor for input. PB0 PB1 PB2~PB3 I/O I/O I/O I/O pin with 10K ohm pull-high resistor for input. Open drain output with 10K ohm pull-high resistor for input. Port B, TTL input level. PB2-PB3 are I/O pins with 35K ohm pull-low resistors for input. PB4~PB7 Vdd Vss I/O Port B, TTL input level Power supply Ground
7. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07~1F Description Indirect Addressing Register Unimplemented PC STATUS MSR Port A Port B Internal RAM, General Purpose Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 3 of 11 2005/6 Ver.1.6
MDT10P41A1
(1) IAR ( Indirect Address Register) : R0 (2) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 (ROM 1K) LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (3) STATUS (Status register) : R3 Bit 0 1 2 3 4 5 Symbol C HC Z PF XX page 0 Carry bit Half Carry bit Zero bit Power loss Flag bit Always read as high Page select bit : 0 : 000H --- 1FFH 1 : 200H --- 3FFH 6X7 XX General purpose bit Function
(4) MSR (Memory Select Register) : R4 (5) PORT A : R5 Bit 3-0 : PA0~PA3, I/O Register 6-4 : Always read as high. 7 : Always read as zero. (6) PORT B : R6 PB7~PB0, I/O Register (7) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" x"0", I/O pin in output mode; x"1", I/O pin in input mode.
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 4 of 11 2005/6 Ver.1.6
MDT10P41A1
(8) EPROM Option by writer programming :
Security bit Weak Disable Disable Enable The default EPROM security is weak disable.
8. Reset Condition for all Registers
Register CPIO A CPIO B IAR PC STATUS MSR PORT A PORT B Address 00h 02h 03h 04h 05h 06h Power-On Reset 1111 1111 1111 1111 1111 1111 0001 1xxx 111x xxxx - 111 xxxx xxxx xxxx
Note : " x "xunknown, " - "xunimplemented, read as "0"
9. Instruction Set
Mnemonic Operands NOP SLEEP RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t
Instruction Code 010000 00000000 010000 00000010 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr
Function No operation Sleep mode Return Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register
Operating None 0/ WT, stop OSC Stack/ PC W/ CPIO r W/ R R/ t I/ W [R(0~3) R(4~7)]/ t R + 1/ t
Status
TF, PF None None None Z None None Z
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 5 of 11 2005/6 Ver.1.6
MDT10P41A1
Instruction Code 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr Mnemonic Operands INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR RLR R, t R, t Function Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Operating R + 1/ t W + R/ t R W/ t (R+/W+1/ t) R 1/ t R 1/ t R a W/ t i a W/ W R a W/ t i a W/ W R o W/ t i o W/ W /R/ t R(n) / R(n-1), C / R(7), R(0)/ C R(n)/ r(n+1), C/ R(0), R(7)/ C 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn Note : W CPIO HC Z C PF PC OSC : : : : : : : : Working register Control I/O port register Half carry Zero flag Carry flag Power loss flag Program Counter Oscillator b: t: Bit position Target 0 : Working register 1 : General register : : : General register address Immediate data ( 8 bits ) Immediate address CLRW CLRR BCR BSR R R, b R, b Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W n JUMP to address 0/ W 0/ R 0/ R(b) 1/ R(b) Skip if R(b)=0 Skip if R(b)=1 n/ PC, PC+1/ Stack LJUMP n CALL RTWI JUMP n i n/ PC n/ PC, PC+1/ Stack Stack/ PC, i/ W n/ PC None None None None Z Z None None None None None Status None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C C
BTSC R, b BTSS R, b LCALL n
R i n
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 6 of 11 2005/6 Ver.1.6
MDT10P41A1
Inclu. Exclu. AND : : : Inclusive `a ' Exclusive `o ' Logic AND `a ' / x : : Complement Don't care
10. Electrical Characteristics
(Operating temperature at 25J).
Sym
Description
Condition
Min 2.3 6.5
Typ
Max 5.5
Unit V MHz
Vdd Operating voltage Fosc Internal RC oscillator frequency Vdd=5V VIL Input Low Voltage PA, PB VIH Input high Voltage PA, PB IIL VOL Input leakage current Output Low Voltage PA, PB Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA VOH Output High Voltage PA, PB Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vpr Power Edge-detector Reset Voltage Vdd=5V Vdd=5V Vdd=5V
7
7.5
-0.6
1.0
V
2.0
Vdd +/-1
V
A
V V
0.5 0.2
4.0 4.7 1.2 1.5
V V V
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 7 of 11 2005/6 Ver.1.6
MDT10P41A1
11. (A)PA0 Equivalent Circuit
PA0: Pull_Hi130K
D
Q
I/O Control
CK
I/O Control Latch
QB
Port I/O Pin D
Write G
Data O/P Latch
Q B
Data Bus QB
D
Read
Data I/P Latch
G
Input Resistor TTL Input Level
(B)PA1~PA3 Equivalent Circuit
Q I/O Control Latch I/O Control CK QB
D
PA1~3: Pull_Hi 50K
Port I/O Pin D Write Data O/P Latch G QB
Data Bus Read
QB G
D Data I/P Latch
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 8 of 11 2005/6 Ver.1.6
MDT10P41A1
12. (A) PB0 Equivalent Circuit
Q I/O Control Latch I/O Control CK QB
D
Pull_Hi 10K
Port I/O Pin D Write Data O/P Latch G QB
Data Bus Read
QB G
D Data I/P Latch
Input Resistor TTL Input Level
(B) PB1 Equivalent Circuit
Q I/O Control I/O Control CK Latch QB
D
Pull_Hi 10K
Port I/O Pin D Write Data O/P Latch G QB
Data Bus Read
QB G
D Data I/P Latch
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 9 of 11 2005/6 Ver.1.6
MDT10P41A1
(C) PB2 ~ PB3 Equivalent Circuit
D I/O Control Latch I/O Control CK
Q
QB
Port I/O Pin D Data O/P Latch G QB PULL- LOW 35 K
Write
Data Bus QB Data I/P Latch G
D Input Resistor TTL Input Level
Read
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 10 of 11 2005/6 Ver.1.6
MDT10P41A1
(D) PB4 ~ PB7 Equivalent Circuit
Q I/O Control I/O Control Latch CK QB
D
Port I/O Pin D Write Data O/P Latch G QB
Data Bus Read
QB G
D Data I/P Latch
Input Resistor TTL Input Level
This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 11 of 11 2005/6 Ver.1.6

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